Doctoral/Postdoctoral Position in Energy-Efficient High-Speed ADCs for Next-Generation Wireline Transceivers

**Doctoral/Postdoctoral Position in Energy-Efficient High-Speed ADCs for Next-Generation Wireline Transceivers** ================================================================================================================ #### **100%, Zurich, fixed-term** The Energy-Efficient Circuits and Intelligent Systems Group (EECIS) at the Department of Information Technology and Electrical Engineering (D-ITET), ETH Zurich, invites applications for a doctoral or postdoctoral position in the area of high-speed, energy-efficient analog-to-digital converters. The position is part of an Innosuisse innovation project, developing a next-generation wireline transceiver for AI data centers. **Project background** ---------------------- AI data centers connect thousands of GPUs, and the links between them have become a bottleneck. Today’s 1.6 Tb/s electrical cables reach less than 3 m, which limits rack design and forces a costly move to optics. The project develops active electrical cables that significantly extend the reach. Instead of raising the symbol rate, it uses a space-time coded signaling scheme that lowers the baud rate, and an ADC-based receiver with digital equalization. In such receivers, the analog-to-digital converter (ADC) is the main bottleneck and often takes the largest share of power and area. Within the project, our group is responsible for the design of the unit ADC. This position focuses on an energy- and area-efficient multi-GS/s SAR ADC with a minimal silicon foot, which serves as the building block of a time-interleaved array. To get there, you will explore new techniques such as aggressive capacitive DAC scaling, loop-unrolled and time-based architectures, background calibration, and merging the receiver front-end with the ADC sampler. **Job description** ------------------- * Develop behavioral models of the ADC and derive its specifications from the link requirements, in close exchange with the industrial partner * Design, layout and tape out the circuits in advanced CMOS technology, and characterize the chips in our measurement lab * Investigate new techniques for high-speed, energy- and area-efficient data conversion, including time-interleaving, calibration and low-jitter clock distribution * Refine the design based on measurement results and support its integration into the transceiver * Publish your results at leading venues of the field and present them at international conferences * Contribute to the teaching activities of the group **Profile** ----------- * Master’s or Ph.D degree in electrical engineering or a closely related field, with excellent grades * Solid background in analog and mixed-signal integrated circuit design * Experience with data converters, in particular SAR or time-interleaved ADCs, is a strong advantage * Hands-on experience with Cadence Virtuoso or similar tools. Previous tape-out or lab measurement experience is a plus * Strong analytical skills and enthusiasm for pushing circuit performance