Doctoral/Postdoctoral Position in Low-Jitter Clock Generation for Single-Photon RGB-D Image Sensors

**Doctoral/Postdoctoral Position in Low-Jitter Clock Generation for Single-Photon RGB-D Image Sensors** ======================================================================================================= #### **100%, Zurich, fixed-term** The Energy-Efficient Circuits and Intelligent Systems Group (EECIS) at the Department of Information Technology and Electrical Engineering (D-ITET), ETH Zurich, invites applications for a doctoral or postdoctoral position in the area of low-jitter frequency synthesis and clock generation. The position is part of an international industry-academia research project developing a next-generation single-chip RGB-D image sensor for robotics. **Project background** ---------------------- Robots in manufacturing need to see colour and depth at the same time, reliably, both indoors and in bright sunlight. Today this usually takes several separate sensors. The project develops a monolithic RGB-D sensor System-on-Chip that combines colour imaging with direct time-of-flight (dToF) depth sensing on a single-photon avalanche diode (SPAD) array. In a dToF sensor, depth is measured from the arrival time of photons. The precision of the clock driving large arrays of parallel time-to-digital converters directly limits depth accuracy. Timing errors of a few picoseconds already turn into visible depth errors. Within the project, our group is responsible for the core analog building blocks of the sensor chip. This position focuses on the on-chip clock generator: a phase-locked loop (PLL) operating at ultra-low jitter at very low power consumption, together with clock synchronization across the sensor array. **Job description** ------------------- * Develop the architecture and system-level specification of a low-jitter, low-power PLL in close exchange with the industrial chip design partner * Investigate new techniques for low-jitter, energy-efficient frequency synthesis and clock distribution for large arrays of time-to-digital converters * Design, layout and tape out the circuits in advanced CMOS technology, and characterize the chips in our measurement lab * Refine the design based on measurement results and support its integration into the sensor SoC * Publish your results at leading venues of the field and present them at international conferences * Contribute to the teaching activities of the group **Profile** ----------- * Master’s or Ph.D degree in electrical engineering or a closely related field, with excellent grades * Solid background in analog and mixed-signal integrated circuit design. Experience with PLLs, oscillators, clock generation or data converters is a strong advantage * Hands-on experience with Cadence Virtuoso or similar tools * Previous tape-out or lab measurement experience is a plus * Strong analytical skills and enthusiasm for pushing circuit performance to its limits * Ability to work independently and in an international team that spans academia and industry * Excellent written and spoken En