Senior NAND/CMOS Device Engineer

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Description Employer: Sandisk GK (Japan) ■Job Description You will be responsible for product and technology development of 3D NAND. Your primary role will be to electrically evaluate and analyze memory cells fabricated on development wafers produced in Yokkaichi, as well as the peripheral circuits and transistors that drive them. Based on these analyses, you will contribute to process development and drive technology development aimed at improving product performance and reliability. You will collaborate with teams across domestic and international sites, including process, test, and design teams, sharing responsibilities and jointly advancing development. Cell Device: Evaluate next-generation flash memory, with a focus on optimizing cell array operating voltages and timing, as well as reliability evaluation Contribute to manufacturing process improvements based on cell array characterization results Perform statistical analysis of variability in mass production cell array characteristics Develop test programs for cell array characterization Develop screening tests to improve early failure (DPPM) rates Conduct failure analysis using electrical methods Collaborate with overseas sites on the above activities Lead product steering toward commercialization CMOS Device: Perform electrical evaluation and analysis of next-generation CMOS (transistors and passive devices) Design TEGs and define design rules for next-generation CMOS development Improve CMOS characteristics toward mass production (reliability and variability improvements, etc.) Conduct electrical evaluation and statistical data analysis (e.g., using Spotfire) to improve yield related to CMOS Develop screening and stress tests to improve DPPM (customer and field failure rate) Serve as an interface between backend sites (overseas) and frontend fabs (domestic) ■Qualifications Required: Multiple years of experience in semiconductor device engineering, failure analysis, or testing - Strong English communication skills are required. While Japanese proficiency is not required at the time of hire, candidates are expected to actively and independently learn Japanese and aim to achieve effective working-level communication in Japanese within approximately two years. Preferred: Strong knowledge and experience in programming languages such as C, C++, Python, and Java - Experience in large-scale data analysis - Work experience with NAND flash or DRAM devices ■仕事概要 3D NANDの製品・技術開発を担当頂きます。 主に四日市の開発ラインで作られたウェハのメモリセル、およびそれを駆動する周辺回路やトランジスタを電気的に測定・解析し、プロセス開発、製品の性能・信頼性向上のための技術開発を行います。 国内、海外他拠点を含むプロセス、テスト、設計等のチームとも仕事を分担して、共同で開発を行います。 ■具体的な業務内容 下記業務をチームで分担します。 Cell Device: 次世代フラッシュメモリ評価。特にセルアレイ動作電圧/タイミングの最適化と信頼性評価 セルアレイ特性評価結果に基づいた製造プロセス改善への貢献 セルアレイ特性の量産ばらつきに関する統計的解析 セルアレイ特性評価テストプログラムの開発 初期故障（DPPM）改善のためのスクリーニング・テストの開発 電気的手法による故障解析 上記に関する海外拠点との協業 製品化のステアリング CMOS Device: 次世代CMOS (トランジスタおよび受動素子)の電気的評価・解析 次世代CMOS開発用TEG設計・Design Rule策定 量産移管に向けたCMOS特性改善(信頼性改善、ばらつき改善など) CMOS起因の製品歩留改善のための電気的評価、Spotfire等を用いた統計データ解析 DPPM(顧客・市場不良率)改善のためのスクリーニング・ストレステストの開発 後工程拠点(海外)と前工程工場(国内)とのインターフェース業務 ＜必須＞ ■数年以上の半導体デバイス/不良解析/テストいずれかの経験 ■英語での技術的な会話・技術レポート作成 ＜歓迎＞ ■C, C++, Python, Java等のコンピュータ言語の深い知識と経験 ■大規模データ分析の経験 ■NANDフラッシュまたはDRAMデバイスでの業務経験 Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less